Google Taps AMD to Co-Design Next-Generation AI Chip

What Happened

Google has engaged AMD to co-design one of its 10th-generation Tensor Processing Units, according to a research note published by semiconductor analysis firm SemiAnalysis. The reported collaboration marks a significant departure from Google's established practice of developing its custom AI accelerators entirely in-house, and signals a potential architectural shift in how the company builds silicon for advanced AI training tasks.

The analysts at SemiAnalysis described the chip as a hybrid AI ASIC, a category that combines application-specific integrated circuit design with more general-purpose processing capability. According to the report, the design may integrate on-package CPU cores intended to support reinforcement learning workloads, a computationally intensive AI training method that has grown in prominence with the development of reasoning-focused AI models.

Background

Google has designed its own TPU line since 2016, when the first generation of the chip entered internal use to accelerate inference workloads across its data centers. Successive generations have expanded the chips' role to cover both training and inference at scale. The current generation, TPU v5, has been available to cloud customers through Google Cloud's infrastructure.

AMD, based in Santa Clara, California, is best known for its Ryzen and EPYC processor lines and its Radeon graphics units. The company has made sustained efforts to position itself in the AI accelerator market through its Instinct GPU line, which competes with Nvidia's dominant H100 and B200 data center products. Collaborating on a customer's proprietary ASIC design represents a different business model from selling discrete accelerators, and would leverage AMD's chip architecture and packaging expertise rather than its finished product catalog.

SemiAnalysis, the firm that published the original note, is a semiconductor research and consulting organization that regularly publishes detailed technical analysis of chip industry supply chains and design trends. The report was subsequently cited and distributed by technology hardware publication Tom's Hardware.

What the Design Involves

The reported hybrid architecture centers on integrating CPU cores directly onto the same package as the AI accelerator die. On-package integration, as opposed to connecting discrete chips via a standard board-level interface, reduces latency between processing units and can improve throughput for workloads that require tight coordination between general-purpose and specialized compute.

Reinforcement learning, the specific workload cited by SemiAnalysis as a design target, involves training AI models through iterative feedback loops in which a model receives reward signals based on the quality of its outputs. This method has been used extensively in training large language models capable of multi-step reasoning, and it places particular demands on memory bandwidth and inter-chip communication that differ from standard transformer training workflows.

The precise division of design responsibilities between Google and AMD, the manufacturing process node, and the intended production timeline were not disclosed in the SemiAnalysis note as reported by Tom's Hardware. Neither Google nor AMD has issued an official public statement confirming the collaboration as of the time of publication.

Industry Context

The reported partnership arrives at a moment when several large technology companies are accelerating custom silicon programs to reduce dependence on merchant AI accelerators, particularly those supplied by Nvidia, which currently holds a dominant share of the data center GPU market. Microsoft, Meta, Amazon, and Apple have each announced or deployed proprietary AI chips within the past two years.

Asia-based chipmakers have also faced constraints in challenging Nvidia's position, with foundry access and advanced packaging capacity identified as key bottlenecks, according to a separate report published this week by The Business Times.

A move by Google to incorporate AMD's design capabilities into its TPU roadmap could influence how other hyperscale cloud operators approach their own chip development strategies, particularly as reinforcement learning workloads grow as a share of total AI compute demand.

Neither Google nor AMD has scheduled a formal announcement related to next-generation TPU development, and the collaboration remains unconfirmed by either company at this time.