Huawei Claims 3D Chip Architecture Can Rival Top Global Silicon

What Happened

Huawei has put forward a new chip architecture based on three-dimensional design that the company says can produce world-competitive semiconductors without relying on the most advanced chipmaking equipment, according to a report by the South China Morning Post published this week. The claim, if substantiated, would represent a significant shift in how China's largest technology company intends to remain competitive in semiconductors under sustained US export restrictions.

The company is describing the approach as a new scaling law, a term borrowed from artificial intelligence research that refers to predictable performance improvements achievable by altering design parameters rather than shrinking transistor sizes through advanced lithography.

Background

Huawei has been subject to sweeping US export controls since 2019, with restrictions tightened in subsequent years to block the company's access to cutting-edge chips and to the equipment used to manufacture them. The controls specifically targeted extreme ultraviolet lithography machines produced by Dutch firm ASML, which are required to fabricate chips at the most advanced process nodes currently in commercial production.

In response, Huawei has pursued a range of alternative strategies. In 2023, the company released the Mate 60 Pro smartphone powered by the Kirin 9000S chip, a 7-nanometer processor manufactured by China's Semiconductor Manufacturing International Corporation using older deep ultraviolet lithography tools. That release drew significant attention from industry analysts and US government officials as evidence that Chinese chipmakers were making progress despite sanctions.

Huawei's new proposal extends that line of development by focusing on how circuits are physically arranged in three-dimensional layers rather than on achieving smaller transistor geometries. The premise is that stacking chiplets or circuit layers vertically can increase computational density and performance in ways that partially compensate for being unable to access sub-3-nanometer fabrication processes.

What the Architecture Involves

The company's 3D scaling law, as described in the South China Morning Post report, posits that performance gains can be achieved by optimising the vertical integration of chip components. Rather than competing directly with TSMC or Samsung on transistor density at the leading edge, Huawei is proposing a design-led path that works within the constraints of equipment available to Chinese manufacturers.

The report does not specify which products will use this architecture first, nor does it provide detailed technical benchmarks comparing performance against chips from leading non-Chinese fabricators. Independent verification of the company's claims has not yet been reported.

Industry Context

Huawei's announcement comes as a separate line of research, reported by ScienceDaily and already covered by this wire service, has demonstrated 3D silicon stacking techniques that researchers say could extend Moore's Law for mainstream chipmakers. The convergence of interest in three-dimensional chip design across both constrained and unconstrained manufacturers reflects broader industry movement away from reliance on traditional planar transistor scaling.

The question of whether Huawei's approach constitutes a genuine technical breakthrough or an effort to reframe existing limitations as a competitive strategy remains open. The South China Morning Post report notes the distinction directly, describing the company's claim as subject to debate among observers.

For US policymakers and chipmakers, the development adds detail to an ongoing discussion about the long-term effectiveness of export controls as a tool for limiting Chinese semiconductor advancement. The US and China held government-level AI and technology talks in recent weeks, according to prior wire reports, though no specific agreements on semiconductor policy were announced from those meetings.

What Comes Next

Huawei has not announced a specific product launch date tied to the new architecture, and independent technical assessments of the 3D scaling claims are expected to emerge as more details become available through patent filings, academic publications, or product releases.